The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 25, 2002
Filed:
Mar. 01, 2001
Chaw Sing Ho, Singapore, SG;
Kheng Chok Tee, Port Klane, MY;
Kin Leong Pey, Singapore, SG;
G. Karunasiri, Singapore, SG;
Soo Jin Chua, Singapore, SG;
Kong Hean Lee, Singapore, SG;
Alex Kalhung See, Singapore, SG;
Chartered Semiconductor Manufacturing Inc., Milpitas, CA (US);
Abstract
A method for forming a void-free epitaxial cobalt silicide (CoSi ) layer on an ultra-shallow source/drain junction. A patterned silicon structure is cleaned using HF. A first titanium layer, a cobalt layer, and a second titanium layer are successively formed on the patterned silicon substrate. The patterned silicon substrate is annealed at a temperature of between about 550° C. and 580° C. in a nitrogen ambient at atmospheric pressure; whereby the cobalt migrates downward and reacts with the silicon structure to form a CoSi /CoSi layer, and the first titanium layer migrates upward and the first titanium layer and the second titanium layer react with the nitrigen ambient to form TiN. The TiN and unreacted cobalt are removed. The silicon structure is annealed at a temperature of between about 825° C. and 875° C. to convert the CoSi /CoSi layer to a CoSi layer. The CoSi layer can optionally be implanted with impurity ions which are subsequently diffused to form ultra-shallow junctions.