The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 17, 2001
Filed:
Dec. 16, 1998
Karey Holland, Phoenix, AZ (US);
Ajoy Zutshi, Chandler, AZ (US);
Fen Dai, Mesa, AZ (US);
Yehiel Gotkis, Gilbert, AZ (US);
C. Jerry Yang, Mesa, AZ (US);
Dennis Schey, Mesa, AZ (US);
Fred Mitchel, Phx., AZ (US);
Lin Yang, Phoenix, AZ (US);
SpeedFam-IPEC, Chandler, AZ (US);
Abstract
A multi-step CMP system is used to polish a wafer to form metal interconnects in a dielectric layer upon which barrier and metal layers have been formed. A first polish removes an upper portion of the metal layer using a first slurry and a first set of polishing parameters, leaving residual metal within the dielectric layer to serve as the metal interconnects. A second polish of the wafer on the same platen and polishing pad removes portions of the barrier layer using a second slurry under a second set of polishing parameters. The second polish clears the barrier layer from the upper surface of the dielectric layer, thereby forming the metal interconnect. To reduce dishing and dielectric erosion, the second slurry is selected so that the barrier layer is removed at a faster rate than the residual metal within the dielectric layer. A cleaning step may be optionally performed between the first and second polishes. Further, the first polish may include a soft landing step to further reduce dishing and dielectric erosion. Alternatively, the first polish may be used to remove portions of the metal and barrier layers, leaving residual metal in the dielectric layer to serve as the metal interconnect. A second polish using a dielectric slurry is then performed to reduce microscratches.