The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 16, 2001
Filed:
Jul. 22, 1999
Tao Cheng Lu, Kaohsiung, TW;
Mam Tsung Wang, Hsinchu, TW;
Chin Hsi Lin, Hsinchu, TW;
Ful Long Ni, Hsinchu, TW;
Macronix International Co., Ltd., Hsinchu, TW;
Abstract
In a virtual ground semiconductor memory device such as an EPROM or a Flash EPROM, a program disturb inhibited unit is operatively connected to a memory array. The memory array includes a plurality of metal virtual ground and bit lines, with at least two bit line selection transistors connected to each of the metal lines. The program disturb inhibited is connected to each virtual ground line and each bit line. In this structure, one metal pitch is connected to two buried diffusion lines. The program inhibited unit includes a plurality of program disturb inhibited transistors, wherein each transistor is connected between a virtual ground and a bit line. A DWL and a DWR dummy line are connected to control the plurality of program disturb inhibited transistors. By combining the program disturb inhibit unit with the memory array, a conventional array structure which has only been suitable for MROM applications can be applied to an EPROM or a Flash EEPROM, allowing the cell size to be reduced.