The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 12, 2000
Filed:
Jul. 27, 1999
Kazuhiko Kajigaya, Iruma, JP;
Kazuyuki Miyazawa, Iruma, JP;
Manabu Tsunozaki, Ohme, JP;
Kazuyoshi Oshima, Ohme, JP;
Takashi Yamazaki, Ohme, JP;
Yuji Sakai, Machida, JP;
Jiro Sawada, Kokubunji, JP;
Yasunori Yamaguchi, Tokyo, JP;
Tetsurou Matsumoto, Higashiyamato, JP;
Shinji Udo, Akishima, JP;
Hiroshi Yoshioka, Akishima, JP;
Hirokazu Saito, Tokorozawa, JP;
Mitsuhiro Takano, Tokorozawa, JP;
Makoto Morino, Akishima, JP;
Sinichi Miyatake, Tokyo, JP;
Eiji Miyamoto, Ohme, JP;
Yasuhiro Kasama, Tokyo, JP;
Akira Endo, Hachioji, JP;
Ryoichi Hori, Tokyo, JP;
Jun Etoh, Hachioji, JP;
Masashi Horiguchi, Kawasaki, JP;
Shinichi Ikenaga, Koganei, JP;
Atsushi Kumata, Kodaira, JP;
Hitachi, Ltd., Tokyo, JP;
Hitachi VSLI Engineering Corp., Tokyo, JP;
Abstract
Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.