The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 14, 2000

Filed:

Mar. 03, 1998
Applicant:
Inventors:

Wen-Yi Hsieh, Hsinchu, TW;

Chi-Rong Lin, Chang Hua Hsien, TW;

Horng-Bor Lu, Hsinchu, TW;

Jenn-Tarng Lin, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
428209 ; 428195 ; 428210 ; 428446 ; 428457 ; 428469 ; 428472 ; 428698 ;
Abstract

A method for forming a barrier/glue layer above the polysilicon layer of a MOS transistor gate comprising the step of providing a semiconductor substrate, and then forming a gate oxide layer above the substrate. Next, a polysilicon layer is formed over the gate oxide layer. Thereafter, a titanium layer is deposited over the polysilicon layer first, and then a titanium nitride layer is deposited above the titanium layer. This titanium/titanium nitride bi-layer is capable of increasing the adhesive strength with a subsequently deposited tungsten silicide layer, and preventing the peeling of the tungsten silicide layer. Furthermore, the titanium nitride layer acts as a barrier for fluorine atoms preventing their diffusion to the gate oxide layer/polysilicon layer interface, and affecting the effective thickness of the gate oxide layer. In the subsequent step, a tungsten suicide layer is formed above the titanium nitride layer. Finally, after an annealing operation, the titanium layer will react with the silicon in the polysilicon layer and the tungsten silicide layer to form a titanium silicide layer. Hence, the resistance of the polycide layer in a MOS transistor gate can be reduced.


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