The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 25, 2000

Filed:

May. 03, 1999
Applicant:
Inventors:

Francis J Carney, Gilbert, AZ (US);

George Amos Carson, Elk Grove Village, IL (US);

Phillip C Celaya, Chandler, AZ (US);

Harry Fuerhaupter, Lombard, IL (US);

Frank Tim Jones, Chandler, AZ (US);

Donald H Klosterman, Gilbert, AZ (US);

Cynthia M Melton, Bolingbrook, IL (US);

James Howard Knapp, Chandler, AZ (US);

Keith E Nelson, Tempe, AZ (US);

Assignee:

Motorola, Inc., Schaumburg, IL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257790 ; 257738 ; 257778 ;
Abstract

A microelectronic package (10) is formed and includes an integrated circuit die (12) attached to a substrate (14) by a plurality of solder bump interconnections (16) to form a preassembly (18). The integrated circuit die (12) has an active face (20) that faces the substrate (14) and is spaced apart therefrom by a gap (22). The integrated circuit die (12) also includes a back face (24) opposite the active face (20). The substrate (14) includes a die attach region (26) and a surrounding region (28) about the integrated circuit die (12). The solder bump interconnections (16) extend across the gap (22) and connect the integrated circuit die (12) and the substrate (14). A mold (30) is disposed about the preassembly (18) such that the mold (30) cooperates with the substrate (14) to define a mold cavity (32) that encloses the integrated circuit die (12). The mold (30) has a molding surface (34) that includes the surrounding region (28) and a mold surface (34) that faces the back face (24) and is spaced apart therefrom. A polymeric precursor (36) is dispensed into the mold cavity (32) and is formed against the molding surface (34) and the back face (24). The polymeric precursor (36) is then cured to form a polymeric encapsulant (38) that encapsulates the integrated circuit die (12).


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