The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 14, 2000
Filed:
Jan. 06, 1998
Tuby Tu, Miali, TW;
Chin-Ta Wu, ChangHua, TW;
Chen Kuang-Chao, Hsinchu, TW;
Dinos Huang, KaoHsiung, TW;
Mosel Vitelic Inc., Hsinchu, TW;
Abstract
A process for intermetal SOG/SOP dielectric planarization without having effect is described. First, a silicon-rich oxide (SRO) layer is formed on a substrate surface. Next, a metal layer and an antireflective coating (ARC) layer are sequentially deposited over the SRO layer. The metal layer and ARC layer are then etched to define metal patterns by the conventional lithography and etching techniques. Next, an Ozone-TEOS (O.sub.3 -TEOS) layer and a SOG layer are then formed over the entire substrate surface. Next, the O.sub.3 -TEOS layer and SOG layer are subjected to etching back treatment to obtain a planar substrate surface which only has a small portion of the O.sub.3 -TEOS layer covered on the substrate surface. The etching back treatment can be PEB, TEB or CMP techniques. Finally, a passivation layer is deposited over the remaining of O.sub.3 -TEOS layer.