The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 13, 1999
Filed:
Jan. 08, 1998
Chie-Ming Yang, Hsin-Chu, TW;
Jih-Wha Wang, Hsin-Chu, TW;
Chien-Jiun Wang, Yung-Ho, TW;
Bou Fun Chen, Taipei, TW;
Liang Szuma, Taipei, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
A method for fabricating polycide gate electrodes wherein voids at the silicide/polysilicon interface are eliminated by ion implantation is described. A layer of gate silicon oxide is grown over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate silicon oxide layer. A silicide layer is formed overlying the polysilicon layer. Silicon ions are implanted into the silicide layer. A hard mask layer is deposited over the silicide layer. Because of the presence of the silicon ions in the silicide layer, silicon atoms from the polysilicon layer do not diffuse into the silicide layer causing voids to form in the polysilicon layer. Therefore, the formation of silicon pits in the semiconductor substrate is prevented. The silicide, polysilicon and gate silicon oxide layers are patterned to complete fabrication of a gate electrode in the manufacture of an integrated circuit device.