The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 26, 1999
Filed:
Sep. 29, 1997
Nicholas F Pasch, Pacifica, CA (US);
Marilyn Hwan, San Carlos, CA (US);
Richard Osugi, Milpitas, CA (US);
Colin Yates, San Jose, CA (US);
Dawn Lee, Morgan Hill, CA (US);
Shumay Dou, San Jose, CA (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A method of providing etched alignment marks on a semiconductor workpiece that has a substantially planar surface, such as one that has been polished, for supporting accurate alignment of the workpiece in subsequent process operations. The surface of the semiconductor workpiece includes two layers of materials that abut at the workpiece surface. For example, the workpiece may include a layer of insulative material such as silicon dioxide forming several vias and a layer of conductive material such as tungsten forming plugs in the vias. The method includes etching the substantially planar surface to reduce a height of one of the materials below the height of the other material. For example, the tungstein plugs can be etched to a height that is below the height of the surrounding silicon dioxide. The location where the silicon dioxide abuts the tungsten produces a small bump. This bump then serves as an alignment mark for subsequent operations. Furthermore, such subsequent operations will replicate, and/or enhance, the topographical distinction of the alignment mark.