Method for making improved polysilicon fet gate electrode structures and

Abstract

A method was achieved for making FET stacked gate electrode structures with improved sidewall profiles. These more vertical sidewalls improve the control tolerance of the gate electrode length (L.sub.eff) and improve the shape of the sidewall spacers for making more reliable metal contacts to the self-aligned source/drain contact areas. The method uses a stacked gate electrode layer having a TEOS oxide and a hard mask of silicon nitride on the gate electrode polysilicon layer. During patterning of the stacked gate electrode structure using a photoresist mask, the hard mask minimizes the buildup of a polymer on the TEOS oxide sidewall. This polymer would otherwise act as a masking material resulting in an abrupt step at the TEOS oxide/polysilicon interface when the polysilicon etch is completed. This results in improved gate electrode line length tolerance and much improved sidewall spacers that minimize electrical shorts between the metal source/drain contacts and the polysilicon gate electrodes.