Scan based testing of an integrated circuit for compliance with timing

Abstract

A method and implementation for providing an improved testable design for an integrated circuit (IC) device. The integrated circuit includes a functional path for the implementation of a functional specification as well as a testing path for testing the timing specifications for the integrated circuit. Input switching devices are connected between input terminals of the IC and inputs to sequential circuit elements, for example flip-flop devices, in the IC. Similarly, output switching devices are connected between outputs of the flip-flop devices and output terminals of the IC. The switching devices are selectively operable to alternately connect the flip-flop devices into either a functional IC path for providing functional output signals during functional cycles, or into a testing IC path for providing testing output signals indicative of timing points throughout the IC during testing cycles. The IC is also operable to selectively disable tristate bus drivers during the testing cycles. The switching devices are arranged such that a single output terminal of the IC may be selectively used to provide both functional and testing output signals.