The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 08, 1998
Filed:
Aug. 09, 1996
Hideo Aoki, Hamura, JP;
Jun Murata, Kunitachi, JP;
Yoshitaka Tadaki, Hannou, JP;
Toshihiro Sekiguchi, Hidaka, JP;
Keizo Kawakita, Ome, JP;
Takashi Hayakawa, Fussa, JP;
Katsutoshi Matsunaga, Fussa, JP;
Kazuhiko Saitoh, Ami-machi, JP;
Michio Nishimura, Tokorozawa, JP;
Minoru Ohtsuka, Fussa, JP;
Katsuo Yuhara, Ami-machi, JP;
Michio Tanaka, Ome, JP;
Yuji Ezaki, Tsuchiura, JP;
Toshiyuki Kaeriyama, Tsukuba-gun, JP;
SongSu Cho, Fujishiro-machi, JP;
Hitachi, Ltd., Tokyo, JP;
Texas Instruments Inc., Dallas, TX (US);
Abstract
The etch-back amount of a silicon oxide film of a memory array which is a higher altitude portion is increased when etching back and flattening the silicon oxide film by arranging a first-layer wiring on a BPSG film covering an upper electrode of an information-storing capacitative element only in a peripheral circuit but not arranging it in the memory array. Thus, a DRAM having a stacked capacitor structure is obtained such that the level difference between the memory array and peripheral circuit is decreased, and the formation of wiring and connection holes are easy.