Physical design automation system and process for designing integrated

Abstract

A process for designing an integrated circuit chip s comprises specifying a plurality of regions on the chip in which a plurality of objects are to be placed, such that there are more of the objects than the regions, and specifying penalties for the objects to be placed in the regions respectively. The objects can be microelectronic cells, interconnect wiring segments, etc. An assignment of the objects to the regions is constructed, and a number of objects for movement between the regions is selected. An optimal permutation of movement of the selected number of objects between the regions is computed such that a cost corresponding to the total penalties for the assignment is maximally reduced, and the assignment is modified by moving the selected number of objects through the optimal permutation. The process steps are repeated iteratively such that a maximum number of objects which will produce a maximal reduction in cost is moved during each iteration. The optimal permutation is determined by computing penalty changes for moving the objects between the regions respectively, defining a penalty change scale having a plurality of subintervals, assigning the objects to the penalty change scale in accordance with their penalty changes, and moving the objects which have penalty changes in a number of subintervals having largest values of negative penalty change.