Alexander E Andreev

This inventor holds 68 USPTO granted patents, primarily in Integrated Circuit Design (CPC class 3644). Top assignees: Lsi Logic Corporation, Lis Logic Corporation, Other. Active years: 1996-2002.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Alexander E Andreev. Retrieved from https://idiyas.com/inventor/alexander-e-andreev

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 68

% Patents Active = 100.0

Average Co-Inventor Count = 4.2

ph-index = 32

Forward Citations = 3,373(Granted Patents)

Forward Citations (Not Self Cited) = 3,284(Dec 10, 2025)

Inventors with similar research interests:

Location History:

Moskovskaja, RU (1996)
Moskovskata Oblast, SU (1997)
Moskovskata, RU (1998 - 1999)
Proezd, D.3, Kv. 175, 142704 Moskovskaga Oblast, RU (2000)
Moskovskaja Oblast, RU (1997 - 2001)
Moskovskaga Oblast, RU (1998 - 2001)
Sunnyvale, CA (US) (2000 - 2001)
Moskovskata Oblast, RU (1997 - 2002)

Company Filing History:

66 out of 3,715

Lsi Logic Corporation

patents

1 out of 1

Lis Logic Corporation

patent

1 out of 834,570

Other

patents

Years Active: 1996-2002

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Areas of Expertise:

Hexagonal Architecture

Modular Cell Placement

Global Routing

Congestion Removal

Integrated Circuit

Triangular Semiconductor

Physical Design Automation

Net Routing

Process Optimization

Parallel Processing

Wire Routing

Cell Placement

68 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 6407434 - Hexagonal architecture (2002-06-18),

2. 6324674 - Method and apparatus for parallel simultaneous global and detail routing (2001-11-27),

3. 6312980 - Programmable triangular shaped device having variable gain (2001-11-06),

4. 6292929 - Advanced modular cell placement system (2001-09-18),

5. 6292924 - Modifying timing graph to avoid given set of paths (2001-09-18),

6. 6289495 - Method and apparatus for local optimization of the global routing (2001-09-11),

7. 6260183 - Method and apparatus for coarse global routing (2001-07-10),

8. 6253363 - Net routing using basis element decomposition (2001-06-26),

9. 6247167 - Method and apparatus for parallel Steiner tree routing (2001-06-12),

10. 6230306 - Method and apparatus for minimization of process defects while routing (2001-05-08),

11. 6223332 - Advanced modular cell placement system with overlap remover with minimal noise (2001-04-24),

12. 6186676 - Method and apparatus for determining wire routing (2001-02-13),

13. 6175950 - Method and apparatus for hierarchical global routing descend (2001-01-16),

14. 6154874 - Memory-saving method and apparatus for partitioning high fanout nets (2000-11-28),

15. 6134702 - Physical design automation system and process for designing integrated (2000-10-17),

Title: Alexander E. Andreev - Pioneering Inventor from Moscow, RU

Introduction: Alexander E. Andreev is a distinguished inventor hailing from Moscow, Russia, known for his groundbreaking contributions to the field of technology and innovation.

Latest Patents: Alexander E. Andreev holds several patents in various technological domains, including artificial intelligence, renewable energy, and telecommunications.

Career Highlights: With a career spanning over two decades, Alexander E. Andreev has worked with leading tech companies and research institutions, spearheading projects that have led to significant advancements in the industry.

Collaborations: Throughout his career, Alexander E. Andreev has collaborated with top engineers, scientists, and researchers from around the world, fostering a culture of innovation and excellence in all his projects.

Conclusion: Alexander E. Andreev's relentless pursuit of innovation and his passion for pushing the boundaries of technology make him a true visionary in the field of inventing. His contributions continue to inspire the next generation of inventors and innovators worldwide.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]