The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 10, 2001
Filed:
Apr. 17, 1998
Pedja Raspopovic, Cupertino, CA (US);
Ranko Scepanovic, San Jose, CA (US);
Alexander E. Andreev, Sunnyvale, CA (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
Nets are routed on an integrated circuit device by dividing a portion of the integrated circuit device into a first group of tiles. A first routing graph is then formed as a function of the first group of tiles and nets are routed as a function of the first routing graph. A new group of tiles is formed by dividing the tiles of the first group of tiles, a new routing graph is formed as a function of the new group of tiles, and nets are rerouted as a function of the new routing graph. The steps of the preceding sentence are then repeated and each time a new group of tiles is formed, the tiles are divided in a same first dimension, resulting in tiles have progressively smaller lengths in that first dimension, while the size of the tiles in a second dimension does not change.