The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 09, 1997
Filed:
Jun. 02, 1995
Sadao Nakashima, Tokyo, JP;
Katsutoshi Izumi, Tokyo, JP;
Norihiko Ohwada, Musashino, JP;
Tatsuhiko Katayama, Hiratsuka, JP;
Komatsu Electronic Metals Co., Ltd., Kanagawa, JP;
Nippon Telegraph and Telephone Corporation, Tokyo, JP;
NIT Electronics Technology Corporation, Tokyo, JP;
Abstract
A SIMOX substrate 1 is processed through high temperature oxidation treatment after forming a mask-pattern 3 to shield specified electrodes from oxidation in order to increase partly a thickness of a buffed oxide layer 2 to form an area 4. Next, after an oxide film is removed from the surface of the substrate and LOCOS separation is practiced, MOSFET is produced by fabricating a source S and a drain D on the area 4 or the buffed oxide layer 2. Since the buried oxide layer corresponding to electrodes parts influenced by disadvantages of parasitic capacitance are thickened, an operation speed of an inverter is not much decreased and since mean thickness of the buried oxide layer can be thinner, a decrease of a drain electric current by negative electrical resistance can be suppressed. Furthermore, since the thickness of the buffed oxide layer can be controlled in response to each device, plural devices having different breakdown voltages are formed together on the same substrate.