The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 16, 1996
Filed:
Feb. 02, 1994
Shuji Ikeda, Koganei, JP;
Koichi Imato, Kodaira, JP;
Kazuo Yoshizaki, Musashimurayama, JP;
Kohji Yamasaki, Akishima, JP;
Soichiro Hashiba, Nagoya, JP;
Keiichi Yoshizumi, Kokubunji, JP;
Yasuko Yoshida, Sayama, JP;
Kousuke Okuyama, Kawagoe, JP;
Mitsugu Oshima, Yamanashi, JP;
Kazushi Tomita, Kawaguchi, JP;
Tsuyoshi Tabata, Yamanashi, JP;
Kazushi Fukuda, Kodaira, JP;
Junichi Takano, Yamanashi, JP;
Toshiaki Yamanaka, Iruma, JP;
Chiemi Hashimoto, Koganei, JP;
Motoko Kawashima, Kodaira, JP;
Fumiyuki Kanai, Houya, JP;
Takashi Hashimoto, Iruma, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
A SRAM having its memory cell constructed to include transfer MISFETs to be controlled by word lines and a flip-flop circuit having driver MISFETs and load MISFETs. Plate electrodes of large area fixed on predetermined power source lines are arranged over the load MISFETs such that the plate electrodes over the offset region of the load MISFETs are formed with an opening. A silicon nitride film having a thickness permeable to hydrogen but not to humidity is formed over the transfer MISFETs and the driver MISFETs formed over the main surface of a semiconductor substrate and the load MISFETs formed of a polycrystalline silicon film deposited on the driver MISFETs.