The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 01, 1992
Filed:
Jun. 08, 1989
Yasuhiro Maeda, Sapporo, JP;
Takashi Yokoyama, Sapporo, JP;
Ichiro Hide, Sapporo, JP;
Takeyuki Matsuyama, Sapporo, JP;
Keiji Sawaya, Sapporo, JP;
Hoxan Corporation, Sapporo, JP;
Abstract
A method of forming a polycrystalline silicon layer on a semiconductor wafer is disclosed having the steps of placing the semiconductor wafers in a predetermined number of recesses formed on a mold body, then creating a mold by securing a mold cover in contact with the front surface of the mold body, rotating the mold by a rotor in the heating inert gas of a melting furnace, maintaining the wafer temperature in the range of 1300.degree. C. to 1350.degree. C., pouring heated melted silicon from an inlet opened at the center of the mold cover into a passage recessed at the center of the mold body, flowing the heated melted silicon radially by centrifugal force to fill the melted silicon in a laminated layer air gap formed between the surface of the wafer placed in the recess and the mold cover, cooling to solidify the melted silicon and obtain a product with the polycrystalline silicon layer formed from the melted silicon on the wafer, and opening the mold cover from the mold body to remove the product from the mold body. Thus, the method can readily form an accumulated layer of the thickness of 100 micron at an extremely high speed with sufficient economy.