The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 1992

Filed:

Apr. 04, 1990
Applicant:
Inventors:

Toshiaki Yamanaka, Hoya, JP;

Naotaka Hashimoto, Hachioji, JP;

Takashi Hashimoto, Hachioji, JP;

Akihiro Shimizu, Akishima, JP;

Koichiro Ishibashi, Tokyo, JP;

Katsuro Sasaki, Fuchu, JP;

Katsuhiro Shimohigashi, Musashimurayama, JP;

Eiji Takeda, Koganei, JP;

Yoshio Sakai, Kanagawa, JP;

Takashi Nishida, Tokyo, JP;

Osamu Minato, Tokyo, JP;

Toshiaki Masuhara, Tokyo, JP;

Shoji Hanamura, Kokubunji, JP;

Shigeru Honjo, Otsuki, JP;

Nobuyuki Moriwaki, Kodaira, JP;

Assignees:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
357 59 ; 357 51 ; 357 233 ; 357 20 ;
Abstract

A semiconductor static random access memory having a high .alpha.-ray immunity and a high packing density is provided which is also capable of high-speed operation. A semiconductor memory device comprises static random access memory cells each including a flip-flop circuit. Storage nodes of each flip-flop circuit have respective pn-junctions formed at regions sandwiched between gate electrodes of first insulated gate field effect transistors and gate electrodes of second insulated gate field effect transistors, respectively. The pn-junction has an area smaller than that of a channel portion of the first or second insulated gate field effect transistor. The gate electrode of one of the two first insulated gate field effect transistors and the drain region of the other insulated gate field effect transistor, on one hand, and the drain region of the one insulated gate field effect transistor and the gate electrode of the other insulated gate field effect transistor, on the other hand, are electrically cross-coupled mutually through first and second electrically conductive films, respectively. Also, to increase packing density and enhance immunity to soft error, the gate electrodes of the first and second insulated gate field effect transistors extend substantially in parallel with one another and the channel regions of the first and second insulated gate field effect transistors extend substantially in parallel with one another.


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