The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2026

Filed:

Sep. 30, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Leonard P. Guler, Hillsboro, OR (US);

Robert Joachim, Beaverton, OR (US);

Shengsi Liu, Portland, OR (US);

Hongqian Sun, Sammamish, WA (US);

Tahir Ghani, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/83 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10W 42/00 (2026.01);
U.S. Cl.
CPC ...
H10D 84/83 (2025.01); H10D 84/0126 (2025.01); H10D 84/038 (2025.01); H10W 42/00 (2026.01);
Abstract

Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for forming a plug between two gates within a transistor layer of a semiconductor device. In embodiments, the plug includes a cap at a top of the plug and a liner surrounding at least a portion of the cap, and a base below the cap and the liner. The cap may include a metal. A top of the cap may be even with, or substantially even with, the top of the two gates. The plug may provide a more even surface at a top of a transistor layer where the plug fills in for a gate cut. Other embodiments may be described and/or claimed.


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Guler, Leonard. (2026). Plug between two gates of a semiconductor device (U.S. Patent No. 12787423). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12787423

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