The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 2026

Filed:

Mar. 11, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Cheng-Wei Chang, Taipei City, TW;

Shahaji B. More, Hsinchu City, TW;

Yi-Ying Liu, Hsinchu City, TW;

Shuen-Shin Liang, Hsinchu County, TW;

Sung-Li Wang, Hsinchu County, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 84/01 (2026.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6735 (2025.01); H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6755 (2025.01); H10D 30/6757 (2025.01); H10D 84/0128 (2025.01); H10D 84/013 (2025.01); H10D 84/0151 (2025.01); H10D 84/038 (2025.01);
Abstract

An exemplary method includes forming a semiconductor fin having a semiconductor layer stack over a semiconductor mesa. The semiconductor layer stack includes a first semiconductor layer, a second semiconductor layer, and the first semiconductor layer is between the semiconductor mesa and the second semiconductor layer. The method further includes forming an isolation feature adjacent the semiconductor mesa and forming a semiconductor cladding layer along a sidewall of the semiconductor layer stack. The semiconductor cladding layer extends below a top surface of the semiconductor mesa and a portion of the isolation feature is between the semiconductor cladding layer and a sidewall of the semiconductor mesa. The method further includes, in a channel region, replacing the first semiconductor layer of the semiconductor fin and the semiconductor cladding layer with a gate stack. The portion of the isolation feature is between the gate stack and the sidewall of the semiconductor mesa.


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Chang, Cheng-Wei. (2026). Isolation for multigate devices (U.S. Patent No. 12777680). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12777680

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