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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12772558 B1

PDFFull Text
Date of Patent:
Oct. 20, 2026

Filed:

Aug. 23, 2023

Domain merger cell to abut power domains for chip area reduction

Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Kamesh Medisetti, Bangalore, IN;

Sharad Kumar Gupta, Bangalore, IN;

Sudesh Chandra Srivastava, Bangalore, IN;

Somesh Agarwal, Noida, IN;

Udayakiran Kumar Yallamaraju, Bangalore, IN;

Anand Ashok Baligatti, Bangalore, IN;

Girish T P, Bangalore, IN;

Ankur Mehrotra, Greater Noida, IN;

Gousulu Kandukuru, Proddatur, IN;

Abhinav Chauhan, Moradabad, IN;

Amit Kashyap, Bangalore, IN;

Parissa Najdesamii, San Diego, CA (US);

Assignee:

QUALCOMM Incorproated, San Diego, CA (US);

Attorney:

Loza & Loza, LLP

Primary Examiner:

Seokjin Kim

Int. Cl.
CPC ...
H10D 84/90 (2025.01);
U.S. Cl.
CPC ...
H10D 84/907 (2025.01); H10D 84/981 (2025.01);
Abstract

A chip includes a merger cell including a first p-type length of diffusion (LOD) region extending in a first direction, a first n-well underneath the first p-type LOD region, a first supply rail configured to receive a first supply voltage, and a first n-tap coupling the first n-well to the first supply rail. The merger cell also includes a second p-type length of diffusion (LOD) region extending in the first direction, a second n-well underneath the second p-type LOD region, a second supply rail configured to receive a second supply voltage different from the first supply voltage, and a second n-tap coupling the second n-well to the second supply rail.

Find Patent Forward Citations

Medisetti, Kamesh. (2026). Domain merger cell to abut power domains for chip area reduction (U.S. Patent No. 12772558). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12772558

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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