Girish T P

Title: Girish T. P. and Chip Area Reduction Through Domain Merger Cells.

Introduction

Girish T. P. is an inventor based in Bengaluru, India, whose patent work includes semiconductor chip design. He is associated with Qualcomm Incorporated and is named on 1 patent in the information provided.

Latest Patents

His listed patent, “Domain Merger Cell to Abut Power Domains for Chip Area Reduction,” describes a chip merger cell designed to support adjacent power domains with different supply voltages. The cell includes two p-type length-of-diffusion regions, each positioned over an n-well and connected through an n-tap to its own supply rail. By accommodating distinct supply voltages within the merger-cell arrangement, the design addresses chip-area reduction.

Career Highlights

The patent reflects work on physical chip design and power-domain integration, where layout choices can affect both area and electrical requirements. The available information identifies Girish T. P. as an inventor associated with Qualcomm Incorporated.

Collaborations

Kamesh Medisetti and Sharad Kumar Gupta are identified as Girish T. P.’s coworkers. The provided details do not specify whether they collaborated with him on this patent.

Conclusion

Girish T. P.’s listed invention focuses on integrating separate power domains in a compact chip layout, highlighting a practical approach to semiconductor area reduction.