Somesh Agarwal

Title: Somesh Agarwal and Chip-Area-Reducing Semiconductor Design.

Introduction

Somesh Agarwal is an inventor based in Noida, India. His patent work includes a semiconductor design intended to reduce chip area by merging cells that abut power domains.

Latest Patents

Agarwal is associated with 1 patent, titled “Domain Merger Cell to Abut Power Domains for Chip Area Reduction.” The invention describes a chip merger cell with two p-type length-of-diffusion regions, each positioned over an n-well. Each n-well is connected by an n-tap to its own supply rail, and the rails receive different supply voltages. This arrangement enables cells associated with separate power domains to abut while supporting a more area-efficient chip layout.

Career Highlights

Agarwal is associated with Qualcomm Incorporated. His patent reflects work on semiconductor layout and power-domain integration, with the stated goal of reducing chip area.

Collaborations

Kamesh Medisetti and Sharad Kumar Gupta are identified as Agarwal’s coworkers. The available information does not specify their roles in the patent or whether they collaborated directly on the invention.

Conclusion

Somesh Agarwal’s patent focuses on a merger-cell design that accommodates distinct power domains while helping reduce semiconductor chip area.