Bengaluru, India

Amit Kashyap

This inventor holds 1 USPTO granted patent. Top assignee: Qualcomm Incorproated. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Amit Kashyap. Retrieved from https://idiyas.com/inventor/amit-kashyap-bdgvwxe1

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Amit Kashyap: Semiconductor Chip Design Inventor.

Introduction

Amit Kashyap is an inventor based in Bengaluru, India. His patent work addresses semiconductor chip layout and power-domain design, with a focus on reducing chip area.

Latest Patents

Kashyap is named on one patent, “Domain merger cell to abut power domains for chip area reduction.” The invention describes a chip merger cell with separate p-type diffusion regions and n-wells connected to supply rails carrying different voltages. By enabling power domains to abut within the chip layout, the design aims to reduce chip area.

Career Highlights

Kashyap is associated with Qualcomm Incorporated. His patent reflects work on physical chip design, including the arrangement of diffusion regions, wells, taps, and supply rails across distinct power domains.

Collaborations

Kamesh Medisetti and Sharad Kumar Gupta are identified as Kashyap’s coworkers. The patent record provided does not specify their roles in the invention.

Conclusion

Amit Kashyap’s patent highlights a semiconductor layout approach for placing different-voltage power domains close together while targeting reduced chip area.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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