The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2026

Filed:

Jun. 06, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Li-Ling Liao, Hsinchu City, TW;

Ming-Chih Yew, Hsinchu City, TW;

Chia-Kuei Hsu, Hsinchu City, TW;

Shin-Puu Jeng, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 70/60 (2026.01); H10P 72/70 (2026.01); H10W 70/05 (2026.01); H10W 70/09 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 74/01 (2026.01); H10W 74/10 (2026.01); H10W 70/652 (2026.01);
U.S. Cl.
CPC ...
H10W 70/614 (2026.01); H10P 72/74 (2026.01); H10W 70/05 (2026.01); H10W 70/09 (2026.01); H10W 70/093 (2026.01); H10W 70/611 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 74/016 (2026.01); H10W 74/117 (2026.01); H10P 72/743 (2026.01); H10W 70/6528 (2026.01);
Abstract

A package structure includes an interposer, a die, a conductive terminal and an interconnection structure that is disposed on a first side of the interposer. The die is electrically bonded to the interposer and disposed over the interconnection structure. The conductive terminal is connected to the interposer and the die via a conductive bump. In order to effectively avoid cold joint issues, round or rectangular polyimide structures are first disposed under the bumps to structurally support the bump and sufficiently increase bump height for improved electrical connection and long term reliability of the package structure.


Find Patent Forward Citations

Liao, Li-Ling. (2026). Method of manufacturing semiconductor packages (U.S. Patent No. 12757759). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12757759

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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