The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2026

Filed:

Aug. 03, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chung-Wei Hsu, Hsinchu, TW;

Kuo-Cheng Chiang, Hsinchu, TW;

Mao-Lin Huang, Hsinchu, TW;

Lung-Kun Chu, New Taipei City, TW;

Jia-Ni Yu, New Taipei City, TW;

Kuan-Lun Cheng, Hsinchu, TW;

Chih-Hao Wang, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 30/69 (2025.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10P 14/20 (2026.01); H10P 14/60 (2026.01); H10P 70/00 (2026.01);
U.S. Cl.
CPC ...
H10D 30/701 (2025.01); H10D 30/031 (2025.01); H10D 30/0415 (2025.01); H10D 30/6735 (2025.01); H10D 30/6739 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01); H10P 14/3462 (2026.01); H10P 14/6308 (2026.01); H10P 70/20 (2026.01);
Abstract

A semiconductor device structure is provided. The device includes one or more first semiconductor layers, and a dipole layer surrounding each first semiconductor layer of the one or more first semiconductor layers, wherein the dipole layer comprises germanium. The structure also includes a capping layer surrounding and in contact with the dipole layer, wherein the capping layer comprises silicon, one or more second semiconductor layers disposed adjacent the one or more first semiconductor layers. The structure further includes a gate electrode layer surrounding each first semiconductor layer of the one or more first semiconductor layers and each second semiconductor layer of the one or more second semiconductor layers.


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