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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12733556 B1

PDFFull Text
Date of Patent:
Sep. 08, 2026

Filed:

Mar. 19, 2024

Offset interposers for large-bottom packages and large-die package-on-package structures

Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Russell K. Mortensen, Chandler, AZ (US);

Robert M. Nickerson, Chandler, AZ (US);

Nicholas R. Watts, Phoenix, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:

Akona IP PC

Primary Examiner:

Pete T Lee

Int. Cl.
CPC ...
H10W 90/00 (2026.01); H05K 1/11 (2006.01); H05K 3/40 (2006.01); H10W 70/05 (2026.01); H10W 70/63 (2026.01); H10W 70/65 (2026.01); H10W 72/00 (2026.01); H10W 72/20 (2026.01); H10W 72/50 (2026.01); H10W 72/90 (2026.01); H10W 70/60 (2026.01); H10W 72/29 (2026.01); H10W 74/15 (2026.01); H10W 90/22 (2026.01);
U.S. Cl.
CPC ...
H10W 90/00 (2026.01); H05K 1/113 (2013.01); H05K 3/4038 (2013.01); H10W 70/05 (2026.01); H10W 70/635 (2026.01); H10W 70/65 (2026.01); H10W 72/00 (2026.01); H10W 72/012 (2026.01); H10W 72/015 (2026.01); H10W 72/019 (2026.01); H10W 72/072 (2026.01); H10W 72/075 (2026.01); H10W 72/20 (2026.01); H10W 72/50 (2026.01); H10W 72/90 (2026.01); H10W 90/401 (2026.01); H10W 90/701 (2026.01); H10W 70/60 (2026.01); H10W 72/244 (2026.01); H10W 72/29 (2026.01); H10W 72/5363 (2026.01); H10W 72/5445 (2026.01); H10W 72/879 (2026.01); H10W 72/884 (2026.01); H10W 72/942 (2026.01); H10W 74/15 (2026.01); H10W 90/22 (2026.01); H10W 90/721 (2026.01); H10W 90/722 (2026.01); H10W 90/724 (2026.01); H10W 90/732 (2026.01); H10W 90/734 (2026.01); H10W 90/754 (2026.01); H10W 90/756 (2026.01); H10W 90/794 (2026.01); Y10T 29/49124 (2015.01);
Abstract

An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.

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