The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2026

Filed:

May. 06, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Su-Chun Yang, Hsinchu County, TW;

Jih-Churng Twu, Hsinchu County, TW;

Jiung Wu, Taoyuan City, TW;

Chih-Hang Tung, Hsinchu, TW;

Chen-Hua Yu, Hsinchu City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 74/10 (2026.01); H10W 74/01 (2026.01); H10W 74/43 (2026.01); H10W 90/00 (2026.01); H10W 70/60 (2026.01); H10W 70/685 (2026.01); H10W 74/00 (2026.01); H10W 74/15 (2026.01); H10W 74/40 (2026.01); H10W 80/00 (2026.01);
U.S. Cl.
CPC ...
H10W 74/147 (2026.01); H10W 74/016 (2026.01); H10W 74/43 (2026.01); H10W 90/00 (2026.01); H10W 70/60 (2026.01); H10W 70/685 (2026.01); H10W 74/00 (2026.01); H10W 74/10 (2026.01); H10W 74/127 (2026.01); H10W 74/15 (2026.01); H10W 74/40 (2026.01); H10W 80/312 (2026.01); H10W 80/327 (2026.01); H10W 90/401 (2026.01); H10W 90/701 (2026.01); H10W 90/722 (2026.01); H10W 90/724 (2026.01); H10W 90/734 (2026.01); H10W 90/754 (2026.01); H10W 90/792 (2026.01);
Abstract

A die stacking structure, a semiconductor package and a method for manufacturing the die stacking structure are provided. The die stacking structure includes a first device die; second device dies, bonded onto the first device die, and arranged side-by-side; a gap profile modifier, laterally enclosing bottommost portions of the second device dies, wherein a thickness of the gap profile modifier gradually decreases away from sidewalls of the second device dies; and a dielectric material, covering the gap profile modifier and laterally surrounding the second device dies.


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