The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2026

Filed:

Jun. 30, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Chia-Ching Lin, Portland, OR (US);

Shriram Shivaraman, Hillsboro, OR (US);

Kevin P. O'brien, Portland, OR (US);

Ashish Verma Penumatcha, Beaverton, OR (US);

Chelsey Dorow, Portland, OR (US);

Kirby Maxey, Hillsboro, OR (US);

Carl H. Naylor, Portland, OR (US);

Sudarat Lee, Hillsboro, OR (US);

Uygar E. Avci, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/47 (2025.01); H10D 30/01 (2025.01); H10D 30/69 (2025.01); H10D 62/80 (2025.01); H10D 64/23 (2025.01);
U.S. Cl.
CPC ...
H10D 30/481 (2025.01); H10D 30/017 (2025.01); H10D 30/0415 (2025.01); H10D 30/701 (2025.01); H10D 62/883 (2025.01); H10D 64/251 (2025.01);
Abstract

Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques directed to creating back end of line 2D transistors that may be used as access transistors for a memory cell. In embodiments, a combination wet etch and dry etch process may be used to form the 2D transistors. Other embodiments may be described and/or claimed.


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