The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 25, 2026
Filed:
Jun. 27, 2022
Intel Corporation, Santa Clara, CA (US);
Nicholas A. Thomson, Hillsboro, OR (US);
Ayan Kar, Portland, OR (US);
Kalyan C. Kolluru, Portland, OR (US);
Benjamin John Orr, Beaverton, OR (US);
Chu-Hsin Liang, Santa Cruz, CA (US);
Biswajeet Guha, Hillsboro, OR (US);
Saptarshi Mandal, Beaverton, OR (US);
Brian Greene, Portland, OR (US);
Sameer Jayanta Joglekar, Hillsboro, OR (US);
Chung-Hsun Lin, Portland, OR (US);
Mauro J. Kobrinsky, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Integrated circuit (IC) devices with diodes formed in a subfin between a support structure of an IC device and one or more nanoribbon stacks are disclosed. To alleviate challenges of limited semiconductor cross-section provided by the subfin, etch depths in the subfin (i.e., depths of recesses in the subfin formed as a part of forming the diodes) are selectively optimized and varied. Deeper recesses are made in subfin portions at which diode terminals (e.g., anodes and cathodes) are formed, to increase the semiconductor cross-section in those portions, thus providing improved subfin contacts. Shallower recesses (or no recesses) are made in subfin portion between the diode terminals, to increase subfin retention. Thus, subfin diodes may be provided in a manner that enables improved diode conductance and/or improved current carrying capabilities while advantageously using substantially the same etch processes as those used for forming nanoribbon-based transistors elsewhere in the IC device.