The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2026

Filed:

Jun. 28, 2024
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Tsung-Han Chuang, Hsinchu, TW;

Zhi-Chang Lin, Hsinchu, TW;

Shih-Cheng Chen, Hsinchu, TW;

Jung-Hung Chang, Hsinchu, TW;

Chien Ning Yao, Hsinchu, TW;

Kuo-Cheng Chiang, Hsinchu, TW;

Chih-Hao Wang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 64/01 (2025.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/66 (2025.01); H10P 14/20 (2026.01);
U.S. Cl.
CPC ...
H10D 64/018 (2025.01); H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6735 (2025.01); H10D 30/6739 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 64/671 (2025.01); H10P 14/3452 (2026.01);
Abstract

A device includes a substrate, a first nanostructure channel above the substrate and a second nanostructure channel between the first nanostructure channel and the substrate. An inner spacer is between the first nanostructure channel and the second nanostructure channel. A gate structure abuts the first nanostructure channel, the second nanostructure channel and the inner spacer. A liner layer is between the inner spacer and the gate structure.


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