The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2026

Filed:

Feb. 03, 2022
Applicant:

Wolfspeed, Inc., Durham, NC (US);

Inventors:

Kyoung-Keun Lee, Cary, NC (US);

Daniel Etter, Durham, NC (US);

Fabian Radulescu, Chapel Hill, NC (US);

Scott Sheppard, Chapel Hill, NC (US);

Daniel Namishia, Wake Forest, NC (US);

Assignee:

WOLFSPEED, INC., Durham, NC (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/15 (2006.01); H01L 31/0256 (2006.01); H10D 30/69 (2025.01); H10P 14/60 (2026.01); H10W 42/00 (2026.01); H10W 74/01 (2026.01); H10W 74/10 (2026.01);
U.S. Cl.
CPC ...
H10W 74/121 (2026.01); H10D 30/792 (2025.01); H10P 14/6339 (2026.01); H10P 14/662 (2026.01); H10W 42/00 (2026.01); H10W 74/01 (2026.01);
Abstract

A semiconductor die includes a semiconductor body, and a multi-layer environmental barrier on the semiconductor body. The multi-layer environmental barrier includes a plurality of sublayers that are stacked on the semiconductor body. Each of the sublayers comprises a respective stress in one or more directions, where the respective stresses of at least two of the sublayers are different. The sublayers may include a first stressor sublayer comprising first stress, and a second stressor sublayer comprising a second stress that at least partially compensates for the first stress in the one or more directions. Related devices and methods of fabrication are also discussed.


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