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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12702042 B1

PDFFull Text
Date of Patent:
Aug. 04, 2026

Filed:

Mar. 16, 2022

Bumps comprising tin, cooper and bismuth for liquid metal socket interconnects

Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Jiaqi Wu, Chandler, AZ (US);

Xiao Lu, Chandler, AZ (US);

Bohan Shan, Chandler, AZ (US);

Valery Ouvarov-Bancalero, Scottsdale, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:

Alliance IP, LLC

Primary Examiner:

Wael M Fahmy

Assistant Examiner:

Aneesa Riaz Baig

Int. Cl.
CPC ...
H10B 43/27 (2023.01); B23K 1/00 (2006.01); B23K 35/26 (2006.01); B23K 101/40 (2006.01); G11C 11/408 (2006.01); G11C 11/412 (2006.01); G11C 11/418 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H10B 41/27 (2023.01); H10B 41/30 (2023.01); H10B 41/35 (2023.01); H10B 43/30 (2023.01); H10B 43/35 (2023.01); H10D 1/00 (2025.01); H10D 1/68 (2025.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 64/27 (2025.01); H10W 72/00 (2026.01); H10W 72/20 (2026.01); H10W 72/29 (2026.01); H10W 72/90 (2026.01); H10W 80/00 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 72/90 (2026.01); B23K 1/0008 (2013.01); B23K 35/26 (2013.01); H10W 72/20 (2026.01); B23K 2101/40 (2018.08); H10W 72/29 (2026.01);
Abstract

In one embodiment, an integrated circuit apparatus comprises a substrate that includes electrical contacts on a first side of the substrate to couple the substrate to an integrated circuit die, a passivation layer on a second side of the substrate opposite the first side, metal pads on the second side of the substrate and within openings defined by the passivation layer, and solder bumps on the metal pads. The solder bumps are a material that is resistant to Gallium-based liquid metal embrittlement.

Find Patent Forward Citations

Wu, Jiaqi. (2026). Bumps comprising tin, cooper and bismuth for liquid metal socket interconnects (U.S. Patent No. 12702042). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12702042

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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