The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 04, 2026
Filed:
Sep. 26, 2022
Intel Corporation, Santa Clara, CA (US);
Leonard P. Guler, Hillsboro, OR (US);
Marie Conte, Hillsboro, OR (US);
Charles H. Wallace, Portland, OR (US);
Robert Joachim, Beaverton, OR (US);
Shengsi Liu, Portland, OR (US);
Saurabh Acharya, Hillsboro, OR (US);
Nidhi Khandelwal, Portland, OR (US);
Kyle T. Horak, Portland, OR (US);
Robert Robinson, Beaverton, OR (US);
Brandon Peters, Darien, IL (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Integrated circuit structures having gate cut plugs removed from trench contacts, and methods of fabricating integrated circuit structures having gate cut plugs removed from trench contacts, are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires. A gate electrode is over the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A gate cut plug extends through the gate electrode and the dielectric sidewall spacer. The gate cut plug extends into but not entirely through the conductive trench contact.