The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 28, 2026
Filed:
May. 09, 2022
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Hsin-Yi Lee, Hsinchu, TW;
Chun-Da Liao, Taipei City, TW;
Cheng-Lung Hung, Hsinchu, TW;
Yan-Ming Tsai, Toufen Township, TW;
Harry Chien, Chandler, AZ (US);
Huang-Lin Chao, Hillsboro, OR (US);
Weng Chang, Hsinchu, TW;
Chih-Wei Chang, Hsinchu, TW;
Ming-Hsing Tsai, Chu-Pei City, TW;
Chi On Chui, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Abstract
A method includes forming a dummy gate stack over a semiconductor region, forming a source/drain region on a side of the dummy gate stack, removing the dummy gate stack to form a trench, forming a gate dielectric layer extending into the trench and on the semiconductor region, and depositing a first work-function layer over the gate dielectric layer. The first work-function layer comprises a metal selected from the group consisting of ruthenium, molybdenum, and combinations thereof. The method further includes depositing a conductive filling layer over the first work-function layer, and performing a planarization process to remove excess portions of the conductive filling layer, the first work-function layer, and the gate dielectric layer to form a gate stack.