The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 21, 2026
Filed:
Sep. 30, 2022
Intel Corporation, Santa Clara, CA (US);
Sukru Yemenicioglu, Portand, OR (US);
Quan Shi, Portland, OR (US);
Marni Nabors, Portland, OR (US);
Charles H. Wallace, Portland, OR (US);
Xinning Wang, Hillsboro, OR (US);
Tahir Ghani, Portland, OR (US);
Andy Chih-Hung Wei, Yamhill, OR (US);
Mohit K. Haran, Forest Grove, OR (US);
Leonard P. Guler, Hillsboro, OR (US);
Sivakumar Venkataraman, Hillsboro, OR (US);
Reken Patel, Portland, OR (US);
Richard Schenker, Portland, OR (US);
INTEL CORPORATION, Santa Clara, CA (US);
Abstract
An integrated circuit includes a first device having a first source or drain region, and a second device having a second source or drain region that is laterally adjacent to the first source or drain region. A conductive source or drain contact includes (i) a lower portion in contact with the first source or drain region, and extending above the first source or drain region, and (ii) an upper portion extending laterally from above the lower portion to above the second source or drain region. A dielectric material is between at least a section of the upper portion of the conductive source or drain contact and the second source or drain region. In an example, each of the first and second devices is a gate-all-around (GAA) device having one or more nanoribbons, nanowires, or nanosheets as channel regions, or is a finFet structure having a fin-based channel region.