The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2026

Filed:

Mar. 31, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;

Inventors:

Wei-Chieh Hsu, Hsinchu, TW;

Han-Hsiang Huang, Hsinchu, TW;

Yu-Sheng Lin, Zhubei City, TW;

Chien-Sheng Chen, Hsinchu, TW;

Shin-Puu Jeng, Po-Shan Village, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 21/48 (2006.01); H10W 70/05 (2026.01); H10W 70/66 (2026.01); H10W 90/00 (2026.01); H10W 74/15 (2026.01);
U.S. Cl.
CPC ...
H10W 90/701 (2026.01); H10W 70/093 (2026.01); H10W 70/66 (2026.01); H10W 90/00 (2026.01); H10W 74/15 (2026.01); H10W 90/724 (2026.01); H10W 90/734 (2026.01);
Abstract

An interconnect structure includes a lower pad including a first conductive layer having a first diameter, and a second conductive layer on the first conductive layer and having a second diameter less than the first diameter, an upper bump on the lower pad and having a third diameter less than the first diameter, and a solder joint between the upper bump and the lower pad.


Find Patent Forward Citations

Quick Actions:

Hsu, Wei-Chieh. (2026). Fine pitch chip interconnect structure for bump bridge and high temperature storage improvement and methods for forming the same (U.S. Patent No. 12685235). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12685235

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