The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2026

Filed:

Jan. 03, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Meng-Hsien Lin, Tainan City, TW;

Hsing-Chih Lin, Tainan City, TW;

Ming-Tsong Wang, Taipei City, TW;

Min-Feng Kao, Chiayi City, TW;

Kuan-Hua Lin, New Taipei City, TW;

Jen-Cheng Liu, Hsin-Chu City, TW;

Dun-Nian Yaung, Taipei City, TW;

Ko Chun Liu, Toufen Township, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 20/40 (2026.01); H10F 39/00 (2025.01);
U.S. Cl.
CPC ...
H10W 20/496 (2026.01); H10F 39/011 (2025.01); H10F 39/809 (2025.01); H10F 39/811 (2025.01);
Abstract

Some embodiments of the present disclosure relate to an integrated chip including an extended via that spans a combined height of a wire and a via and that has a smaller footprint than the wire. The extended via may replace a wire and an adjoining via at locations where the sizing and the spacing of the wire are reaching lower limits. Because the extended via has a smaller footprint than the wire, replacing the wire and the adjoining via with the extended via relaxes spacing and allows the size of the pixel to be further reduced. The extended via finds application for capacitor arrays used for pixel circuits.


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