Three-dimensional memory devices having isolation structure for source select gate line and methods for forming the same

Abstract

Embodiments of three-dimensional (3D) memory devices are disclosed. In an example, a 3D memory device includes a semiconductor layer, a memory stack over the semiconductor layer, first channel structures each extending vertically through the memory stack in an edge region, and an isolation structure. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. At least one of conductive layers toward the semiconductor layer is a source select gate line (SSG). The isolation structure extends vertically through the SSG and into the semiconductor layer. The memory stack includes a core array region, a staircase region, and the edge region being laterally between the core array region and the staircase region. At least one of the first channel structures extends through the isolation structure and is separated from the SSG through the isolation structure.