The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2026

Filed:

Jul. 28, 2021
Applicant:

United Microelectronics Corp., Hsin-Chu City, TW;

Inventors:

Wei-Ren Huang, Changhua County, TW;

Chen-Hsiao Wang, Hsinchu City, TW;

Kai-Kuang Ho, Hsinchu City, TW;

Assignee:

UNITED MICROELECTRONICS CORP., Hsin-Chu City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10P 54/00 (2026.01); H10P 50/00 (2026.01); H10P 50/24 (2026.01); H10P 74/00 (2026.01);
U.S. Cl.
CPC ...
H10P 54/00 (2026.01); H10P 50/242 (2026.01); H10P 50/691 (2026.01); H10P 50/73 (2026.01); H10P 74/273 (2026.01);
Abstract

A wafer with a test structure includes a wafer with a front side and a back side. A first die, a second die, a third die and a scribe line are disposed on the wafer. The scribe line is positioned between the dice. The first die includes a first dielectric layer and a first metal connection disposed within and on the first dielectric layer. A test structure and a dielectric layer are disposed on the scribe line, wherein the test structure is on the dielectric layer. Two first trenches are respectively disposed between the first dielectric layer and the dielectric layer and disposed at one side of the dielectric layer. Two second trenches penetrate the wafer, and each of the two second trenches respectively connects to a corresponding one of the two first trenches. A grinding tape covers the front side of the wafer and contacts the test structure.


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