The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2026

Filed:

Nov. 30, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Jin Yang, Hillsboro, OR (US);

David Shia, Portland, OR (US);

Adel A. Elsherbini, Tempe, AZ (US);

Christopher M. Pelto, Beaverton, OR (US);

Kimin Jun, Portland, OR (US);

Bradley A. Jackson, Lake Oswego, OR (US);

Robert J. Munoz, Round Rock, TX (US);

Shawna M. Liff, Scottsdale, AZ (US);

Johanna M. Swan, Scottsdale, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 72/00 (2026.01); H10W 72/20 (2026.01); H10W 74/15 (2026.01);
U.S. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 72/07232 (2026.01); H10W 72/07236 (2026.01); H10W 72/07254 (2026.01); H10W 72/247 (2026.01); H10W 74/15 (2026.01); H10W 90/722 (2026.01); H10W 90/724 (2026.01); H10W 90/732 (2026.01); H10W 90/792 (2026.01);
Abstract

A microelectronic assembly is provided, comprising: a first IC die coupled to a surface with first interconnects having a first pitch; and a second IC die coupled to the surface with second interconnects having a second pitch. The second pitch is greater than the first pitch, and the first pitch is less than 10 micrometers. In another embodiment, a microelectronic assembly is provided, comprising: a first stack coupled to a surface, the first stack comprising a first number of IC dies; and a second stack coupled to the surface, the second stack comprising a second number of IC dies, in which: the first stack and the second stack are laterally surrounded by a dielectric, the first stack and the second stack have a same thickness, and the first number is less than the second number.


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