Method of forming a memory cell having an offset interconnect via extending through a hard mask with variable thickness

Abstract

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a lower insulating structure disposed over a lower dielectric structure surrounding an interconnect. The lower insulating structure has sidewalls extending through the lower insulating structure. A bottom electrode is arranged along the sidewalls and an upper surface of the lower insulating structure, a data storage structure is disposed on first interior sidewalls and an upper surface of the bottom electrode, and a top electrode is disposed on second interior sidewalls and an upper surface of the data storage structure. An interconnect via is on an upper surface of the top electrode. A bottom surface of the bottom electrode is laterally outside of a bottom surface of the interconnect via.