The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2026

Filed:

Dec. 29, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Mahmut Sami Kavrik, Eugene, OR (US);

Carl Naylor, Portland, OR (US);

Chelsey Dorow, Portland, OR (US);

Chia-Ching Lin, Portland, OR (US);

Dominique Adams, Portland, OR (US);

Kevin O'brien, Portland, OR (US);

Matthew Metz, Portland, OR (US);

Scott Clendenning, Portland, OR (US);

Sudarat Lee, Hillsboro, OR (US);

Tristan Tronic, Aloha, OR (US);

Uygar Avci, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01); H01L 21/28 (2025.01); H01L 21/3213 (2006.01); H10D 30/67 (2025.01); H10D 64/01 (2025.01); H10D 64/62 (2025.01); H10P 50/26 (2026.01); H10D 62/80 (2025.01); H10D 62/85 (2025.01);
U.S. Cl.
CPC ...
H10D 64/01 (2025.01); H10D 30/673 (2025.01); H10D 30/6734 (2025.01); H10D 30/6737 (2025.01); H10D 30/675 (2025.01); H10D 64/011 (2026.01); H10D 64/0114 (2026.01); H10D 64/01358 (2026.01); H10D 64/01364 (2026.01); H10D 64/62 (2025.01); H10P 50/267 (2026.01); H10D 30/6736 (2025.01); H10D 30/6739 (2025.01); H10D 62/80 (2025.01); H10D 62/8503 (2025.01); H10D 62/882 (2025.01);
Abstract

Devices, transistor structures, systems, and techniques, are described herein related to selective gate oxide formation on 2D materials for transistor devices. A transistor structure includes a gate dielectric structure on a 2D semiconductor material layer, and source and drain structures in contact with the gate dielectric structure and on the 2D semiconductor material layer. The source and drain structures include a metal material or metal nitride material and the gate dielectric structure includes an oxide of the metal material or metal nitride material.


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