The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2026

Filed:

Nov. 03, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chen-Shien Chen, Zhubei, TW;

Chi-Yen Lin, Tainan, TW;

PO-Chen Chen, Hsinchu, TW;

Wu-An Weng, Hsinchu, TW;

Hsu-Hsien Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/49 (2006.01); H01L 21/02 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 23/49816 (2013.01); H01L 21/02052 (2013.01); H01L 21/6836 (2013.01); H01L 24/05 (2013.01); H01L 24/97 (2013.01); H01L 25/0655 (2013.01); H01L 2224/05025 (2013.01); H01L 2224/97 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/18161 (2013.01);
Abstract

A package includes a first integrated circuit die and a second integrated circuit die over and bonded to the first integrated circuit die. A first surface region of the second integrated circuit die is hydrophobic, and the first integrated circuit die and the second integrated circuit die are bonded together with dielectric-to-dielectric bonds and metal-to-metal bonds. The package further includes a first insulating material over the first integrated circuit and surrounding the second integrated circuit die. The first insulating material contacts the first surface region.


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