The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 02, 2026
Filed:
Jan. 05, 2023
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Chih-Wei Wu, Zhuangwei Township, TW;
Ying-Ching Shih, Hsinchu City, TW;
Wen-Chih Chiou, Zhunan Township, TW;
An-Jhih Su, Taoyuan City, TW;
Chia-Nan Yuan, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Abstract
A system on chip (SoC) die package is attached to a redistribution structure of a semiconductor device package such that a top surface of the SoC die package is above a top surface of an adjacent memory die package. This may be achieved through the use of various attachment structures that increase the height of the SoC die package. After encapsulating the memory die package and the SoC die package in an encapsulation layer, the encapsulation layer is grinded down. The top surface of the SoC die package being above the top surface of the adjacent memory die package results in the top surface of the SoC die package being exposed through the encapsulation layer after the grinding operation. This enables heat to be dissipated through the top surface of the SoC die package.