The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2026

Filed:

May. 09, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;

Inventors:

Yu-Hsiang Yang, Tainan, TW;

Chen-Ming Huang, Tainan, TW;

PO-Wei Liu, Tainan, TW;

Shih-Hsien Chen, Zhubei, TW;

Hung-Ling Shih, Tainan, TW;

Chang Hung-Chang, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 41/60 (2023.01); H01L 21/768 (2006.01); H10D 30/68 (2025.01); H10D 30/69 (2025.01);
U.S. Cl.
CPC ...
H10B 41/60 (2023.02); H01L 21/76843 (2013.01); H10D 30/6891 (2025.01); H10D 30/711 (2025.01);
Abstract

A field effect transistor includes a source region and a drain region embedded in a portion of a semiconductor substrate; a gate dielectric overlying a channel region located between the source region and the drain region; a gate electrode overlying the gate dielectric; a dielectric gate liner laterally surrounding the gate electrode; a inner gate spacer laterally surrounding the dielectric gate liner; a contoured gate capping dielectric including a vertically-extending portion that laterally surrounds the inner gate spacer and a horizontally-extending portion that overlies the gate electrode; and a outer gate spacer laterally surrounding the contoured gate capping dielectric.


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