The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2026

Filed:

Jun. 30, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Abhishek Anil Sharma, Portland, OR (US);

Tahir Ghani, Portland, OR (US);

Anand S. Murthy, Portland, OR (US);

Cory Weber, Hillsboro, OR (US);

Rishabh Mehandru, Portland, OR (US);

Wilfred Gomes, Portland, OR (US);

Sagar Suthram, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 20/41 (2026.01); H10D 30/62 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01); H10W 20/00 (2026.01); H10W 20/20 (2026.01);
U.S. Cl.
CPC ...
H10W 20/427 (2026.01); H10D 30/62 (2025.01); H10D 84/0186 (2025.01); H10D 84/038 (2025.01); H10D 84/853 (2025.01); H10W 20/023 (2026.01); H10W 20/20 (2026.01);
Abstract

Structures having vertical keeper or power gate for backside power delivery are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a plurality of fin-based transistors, and a plurality of metallization layers above the fin-based transistors of the device layer. A backside structure is below the fin-based transistors of the device layer. The backside structure includes a ground metal line. One or more vertical gate all-around transistors is between the fin-based transistors of the device layer and the ground metal line of the backside structure.


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