The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 19, 2026
Filed:
Jun. 28, 2022
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Abhishek Anil Sharma, Portland, OR (US);
Wilfred Gomes, Portland, OR (US);
Anand S. Murthy, Portland, OR (US);
Tahir Ghani, Portland, OR (US);
Sagar Suthram, Portland, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); H01L 23/528 (2006.01); H10D 30/01 (2025.01); H10D 64/01 (2025.01); H10D 84/85 (2025.01); H10D 86/00 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6735 (2025.01); H01L 23/528 (2013.01); H10D 30/014 (2025.01); H10D 30/031 (2025.01); H10D 64/01 (2025.01); H10D 84/85 (2025.01); H10D 86/201 (2025.01);
Abstract
Structures having AOI gates with routing across nanowires are described. In an example, an integrated circuit structure includes a stack of horizontal nanowires along a vertical direction. A gate stack is over the stack of horizontal nanowires and is surrounding a channel region of each of the horizontal nanowires, the gate stack having one or more cuts in the vertical direction.