The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2026

Filed:

Feb. 25, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Abhishek A. Sharma, Hillsboro, OR (US);

Tahir Ghani, Portland, OR (US);

Anand S. Murthy, Portland, OR (US);

Wilfred Gomes, Portland, OR (US);

Sagar Suthram, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 23/38 (2006.01); H01L 23/473 (2006.01); H01L 25/18 (2023.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 23/38 (2013.01); H01L 23/473 (2013.01); H01L 25/18 (2013.01); H01L 2225/06589 (2013.01);
Abstract

Described herein are memory devices that include a cooling structure for cooling one or more memory arrays. The memory arrays may be static random access memory (SRAM) arrays formed in multiple layers as a stacked memory device. The cooling structure may cool one or more layers of an SRAM device. For example, a cooling structure may be formed around the SRAM device and coupled to a cooling device. Alternatively, a cooling layer may be included in a memory device and coupled to one or more thermal interface layers in thermal contact with a memory layer by cold vias. The cold vias transfer a cold temperature from the cooling layer to the thermal interface layer to cool the thermal interface layer and, in turn, the memory arrays.


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